Integrated circuits continue to increase in size, use, and complexity. For example, integrated circuit memories are used in business and personal devices. With each of the above factors, there is an ongoing need to design and manufacture such integrated circuits as efficiently as possible, minimizing cost and size while maximizing reliability. The present invention balances each of these goals in the context of an integrated circuit having numerous polysilicon layers and at least one metal layer, all of which are typically separated by respective dielectric layers.
Current static random access memory ("SRAM") integrated circuits are constructed in the manner set forth above, that is, with numerous layers of polysilicon, dielectric, and/or metal. As known in the art, the successive polysilicon and/or metal layers are often referred to with corresponding numeric references so as to distinguish successive layers as they rise in ascending fashion from the underlying semiconductor substrate. Thus, the polysilicon layer which is first encountered but over the semiconductor substrate is often referred to as a "poly-1" layer, while the polysilicon layer which is second encountered and over the semiconductor substrate and the poly-1 layer is often referred to as a "poly-2" layer, and so forth. As the number of polysilicon, dielectric, and/or metal layers increases, so does the complexity of design rules. The design rules also relate to other features, such as the decreasing size of gate conductors, variations in fabrication processes, and other considerations known in the art.
Given the above backdrop, FIGS. 1a through 1c illustrate a cross-sectional view of a prior art method of fabricating an integrated circuit which further demonstrates certain problems recognized by the inventor of the present invention. Turning first to FIG. 1a, the structure shown in that figure depicts a portion of an integrated circuit that has been partially fabricated, and which includes a silicon substrate 10 with a surface 10a. Further, field oxide regions 12a, 12b, and 12c are formed along surface 10a. Various items may be formed by a poly-1 layer on surface 10a. For example, in FIG. 1a, a first transistor gate 14a is formed on surface 10a between regions 12a and 12b, and a second transistor gate 14b is formed on surface 10a between regions 12b and 12c. Transistor gates 12a and 12b are formed as known in the art, and may include capping layers as part of the gate structure. In addition to poly-1 structures on surface 10a, other items may be formed by portions of the poly-1 layer overlying the field oxide regions. For example, a conductor 14c is formed immediately overlying field oxide region 12c. Each of items 14a through 14c are formed by depositing the poly-1 layer and etching according to known techniques. In addition, note that when used throughout this document, the "poly" layers may be formed by polysilicon, or may be polycides, that is, the combination of polysilicon and a refractory metal silicide.
With further reference to FIG. 1a, an interlevel dielectric layer 16 is formed over the structures described above. Typically, dielectric layer 16 is a deposited oxide on the order of 900 to 3,000 angstroms in thickness. After dielectric layer 16 is formed, holes are formed through that layer, typically using standard masking and etching techniques. For purposes of illustration, the locations of these holes are shown using vertical dotted lines in layer 16, and are numbered 18a through 18e. Holes 18a through 18e are commonly on the order of 0.5 microns in diameter. As described later, holes 18a through 18e are thereafter filled with conductive material so electrical contact may be made to the component underlying the hole. For example, a conductive contact may be formed through hole 18a to surface 10a so that electrical contact may be made to the diffused region (not specifically shown) immediately to the side of first transistor gate 14a.
FIG. 1b illustrates the electrical contacts 20a through 20e through dielectric layer 16 as described above. Contacts 20a through 20e are formed first by depositing a conductive layer and second by selectively etching that layer to form the desired size and shape of the contacts. Particularly, a blanket poly-2 layer is formed using a chemical vapor deposition ("CVD") technique. Typically, the CVD layer is conformal and its thickness is selected to fill the largest diameter among holes 18a through 18e. Thereafter, the CVD layer is patterned and etched using known techniques. With specific reference to the contacts, FIG. 1b includes poly-2 contacts 20a through 20e formed in holes 18a through 18e, respectively, from FIG. 1a. In the current example, contacts 20a through 20e form electrical points to be contacted by subsequent conductive layers. In addition, poly-2 may be used to form "landing pads" as that term is known in the art. Note further that contacts 20d and 20e are also connected to one another, thereby forming a so-called local interconnect as known in the art.
With further reference to FIG. 1b, a planarized dielectric layer 22 is formed over the structures described above, including the poly-2 contacts 20a through 20e. Note that while dielectric layer 22 covers two polysilicon layers, in many current instances a poly-3 layer (and an additional interlevel oxide layer) is also included before a layer such as dielectric layer 22 is formed. Thus, in common prior art situations, the formation of a planarized dielectric layer does not occur until after the final polysilicon layer is already formed, particularly in the formation of static random access memories.
Returning to dielectric layer 22, that layer is typically an oxide on the order of 5,000 to 10,000 angstroms in thickness. After dielectric layer 22 is formed, holes are formed through that layer, again using standard masking and etching techniques. For purposes of illustration, the locations of these holes are shown using vertical dashed lines in layer 22, and are numbered 24a through 24d. Holes 24a through 24d are commonly on the order of 0.5 microns in diameter.
FIG. 1c illustrates the electrical contacts through dielectric layer 22. Particularly, holes 24a through 24d are commonly filled with a metal so electrical contact may be made to the component underlying the hole. For example, a metal layer 26 is formed overlying the structure of FIG. 1b, thereby filling holes 24a through 24d described in connection with FIG. 1b. As a result, metal layer 26 provides electrical interconnection to the components contacted within holes 24a through 24d.
To better appreciate the invention described below, various points are set forth here with respect to FIGS. 1a through 1c. First, note that the length of holes 24a through 24d, as defined through layer 22, differs because the vertical height of the various contact areas differ; for example, contact pad 20a is vertically lower than is contact pad 20b. Consequently, hole 24a extends farther through dielectric layer 22 than does holes 20b. Second, holes 24a through 24d have a high aspect ratio (i.e., the ratio of the hole length relative to its diameter). Third, as known in the art, holes with higher aspect ratios increase design complexity for subsequent layers. For example, when metal layer 26 is applied to the high aspect ratio holes, layer 26 must be sufficiently thick in order to fully fill those holes. In other words, a relatively deep and narrow hole creates additional design complexities, but this must be addressed, particularly to form a sufficient barrier against silicon and metal interdiffusion.
It is therefore an object of the present invention to provide an integrated circuit with a planarized dielectric layer between successive polysilicon layers which overcomes and improves upon the disadvantages and drawbacks of the prior art.
It is a further object of the present invention to provide such an integrated circuit which reduces the aspect ratio of holes having a metal passing through those holes.
It is a further object of the present invention to provide such an integrated circuit which decreases design complexity for the circuit.
It is a further object of the present invention to provide such an integrated circuit which provides an improved formation of the metalization layer within contact holes as compared with the prior art.
It is a further object of the present invention to provide such an integrated circuit which may be used in constructing a static random access memory.
Still other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having references to the following specification together with its drawings.